1. Field of the Invention
The present invention relates to binary counter circuits, and in particular, to Gray Code counter circuits.
2. Description of the Related Art
Binary counters are used in virtually every digital computer or programmable controller, as well as many other types of digital systems. Many binary counters count sequentially, up or down, in accordance with a normal binary sequence. However, counting in a normal binary sequence results in bit pattern changes having multiple bit transitions. With multiple bits all experiencing logical transitions at one time, a binary counter can experience transition errors, e.g., "glitches," and produce electrical noise, thereby causing interference within the host system.
To overcome these problems, Gray Code counters are often used. Gray Code counters have the advantage of producing only one bit transition from one count to the next, thereby producing a virtually glitch-free count sequence.
However, Gray Code counters have problems of their own. Unlike binary counters, whose individual bit transitions are dependent only upon the logical states of their immediately adjacent bits, a Gray Code counter's individual bit transitions are dependent upon the logical state of all other bits within the counter. This has resulted in complex logic and circuit designs based upon complex logic equations representing the expressions or states of the counter required to define the counting sequence. Such complexity increases greatly as more bits are added, i.e., for longer count sequences. Furthermore, the complexity is exacerbated for Gray Counters designed to provide both up and down counting, i.e., incrementing and decrementing count sequences.
The complexity of Gray Code counters has been caused by the interdependency of the individual counter bits' transitions upon the logical states of all the other counter bits. Such interdependency has produced designs having interconnections for feedback and feedforward paths coupling to or across multiple counter stages. This causes the interconnections to differ from one stage to the next.
Many Gray Code counter designs use clock signals for the individual counter stages which are not fully synchronous. These asynchronous counters use various means for gating the counter stages clock signals. Other Gray Code counters have been designed to operate completely asynchronously with no clock signal per se. Instead, these Gray Code counters operate as ripple counters.
A Gray Code counter's interstage connections are further affected when the counter is designed to provide both incrementing and decrementing count sequences. In this case, several, if not most, counter stages must usually be interconnected.
The inter-bit dependence of Gray Code counters has resulted in counter designs which tend to be unique to each particular application, and must generally be redesigned whenever a bit or bits are to be added to or removed from the count sequence. Such redesign has been further necessitated when it is desired that the Gray Code counter selectively increment or decrement during its count sequence.
Furthermore, the inter-bit dependence of Gray Code counters has caused this uniqueness of design to extend all the way down to the individual counter stages. The interfaces among the counter stages, including the clock signals, vary from one counter stage to the next. As a result, prior art Gray Code counter designs have been either non-modular or non-synchronous, or both.
Thus, it would be desirable to have a Gray Code counter design which is modular so that bits may be simply added to or removed from the count sequence by merely adding or removing counter stage modules without affecting the respective interfaces among the remaining counter stages. It would be further desirable to have such a Gray Code counter design which is also fully synchronous. It would be still further desirable to have such a synchronous, modular Gray Code counter design which can be selectively programmed to count up or down, i.e., increment or decrement during its count sequence.